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Prof. Dr. Ali Ziya Alkar’s Project Receives TÜBİTAK 1001 Support: Deterministic Neuroplasticity on FPGA
August 9, 2026
The project titled “Deterministic Neuroplasticity: Adaptive Acoustic Anomaly Detection via Real-Time Intrinsic Hardware Evolution on FPGAs”, led by our faculty member Prof. Ali Ziya Alkar, has been awarded funding under the TÜBİTAK ARDEB 1001 program.
The project aims to develop a new hardware architecture that enables Industrial Internet of Things (IIoT) and Edge AI systems to adapt to changing field conditions. Artificial intelligence models trained under controlled laboratory conditions may gradually lose accuracy and reliability when exposed to real-world variations such as sensor aging, changing acoustic environments, or the introduction of new machinery. This phenomenon, known as “concept drift,” presents a major challenge for industrial applications that require continuous and dependable operation.
To address this problem, the project will develop a novel Intrinsic Hardware Evolution approach based on Partial Reconfiguration technology on IoT-oriented FPGA platforms. One of the project’s key innovations, the “Deterministic Neuroplasticity” model, is designed to allow AI hardware to reorganize its own structure in response to changing conditions. Unlike conventional evolvable hardware approaches, the proposed system will construct new hardware topologies by combining pre-verified CNN and MLP building blocks in a modular and predictable manner. This “Lego-like” architecture is intended to reduce hardware adaptation times to the order of seconds, enabling near real-time response to changing industrial environments.
The system will continuously monitor model reliability and, when a degradation in performance is detected, securely capture and buffer the relevant new data. Candidate architectures will be evaluated using pre-characterized cost tables for energy consumption and latency, avoiding the need to physically deploy and test every alternative. During optimization, newly observed data will also be evaluated together with a fixed reference validation dataset, helping the system adapt to emerging conditions while preserving previously acquired capabilities and overall reliability.
By eliminating cloud dependency and targeting approximately 30% higher energy efficiency compared with GPU-based solutions, the proposed architecture is expected to support privacy-preserving, energy-efficient, and adaptive AI directly at the edge. The project is also expected to contribute to the development of high-value-added domestic FPGA IP technologies and strengthen research capacity at the intersection of reconfigurable hardware and Edge AI. The research team welcomes new academic and industrial collaborations, as well as enthusiastic researchers interested in contributing to the challenging problems addressed by the project.
We congratulate our faculty member and his team for this prestigious project and wish them success in their work.
To address this problem, the project will develop a novel Intrinsic Hardware Evolution approach based on Partial Reconfiguration technology on IoT-oriented FPGA platforms. One of the project’s key innovations, the “Deterministic Neuroplasticity” model, is designed to allow AI hardware to reorganize its own structure in response to changing conditions. Unlike conventional evolvable hardware approaches, the proposed system will construct new hardware topologies by combining pre-verified CNN and MLP building blocks in a modular and predictable manner. This “Lego-like” architecture is intended to reduce hardware adaptation times to the order of seconds, enabling near real-time response to changing industrial environments.
The system will continuously monitor model reliability and, when a degradation in performance is detected, securely capture and buffer the relevant new data. Candidate architectures will be evaluated using pre-characterized cost tables for energy consumption and latency, avoiding the need to physically deploy and test every alternative. During optimization, newly observed data will also be evaluated together with a fixed reference validation dataset, helping the system adapt to emerging conditions while preserving previously acquired capabilities and overall reliability.
By eliminating cloud dependency and targeting approximately 30% higher energy efficiency compared with GPU-based solutions, the proposed architecture is expected to support privacy-preserving, energy-efficient, and adaptive AI directly at the edge. The project is also expected to contribute to the development of high-value-added domestic FPGA IP technologies and strengthen research capacity at the intersection of reconfigurable hardware and Edge AI. The research team welcomes new academic and industrial collaborations, as well as enthusiastic researchers interested in contributing to the challenging problems addressed by the project.
We congratulate our faculty member and his team for this prestigious project and wish them success in their work.
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